gitaskhub
andres-mancera/ethernet_10ge_mac_sv_uvm_tb↗

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

Stars · 163
Language · Verilog
Ask anything about this repo to start.
Full explanation on explaingit →

By chatting or signing in you agree to the Terms and chat-message logging (revocable in History).